if ( type == MAP_PIRQ_TYPE_GSI )
{
- for ( i = 16; i < NR_PIRQS; i++ )
+ for ( i = 16; i < NR_IRQS; i++ )
if ( !d->arch.pirq_vector[i] )
break;
- if ( i == NR_PIRQS )
+ if ( i == NR_IRQS )
return -ENOSPC;
}
else
{
- for ( i = NR_PIRQS - 1; i >= 16; i-- )
+ for ( i = NR_IRQS - 1; i >= 16; i-- )
if ( !d->arch.pirq_vector[i] )
break;
if ( i == 16 )
if ( !IS_PRIV(current->domain) )
return -EPERM;
- if ( pirq < 0 || pirq >= NR_PIRQS || vector < 0 || vector >= NR_VECTORS )
+ if ( pirq < 0 || pirq >= NR_IRQS || vector < 0 || vector >= NR_VECTORS )
{
dprintk(XENLOG_G_ERR, "dom%d: invalid pirq %d or vector %d\n",
d->domain_id, pirq, vector);
int vector, ret = 0;
bool_t forced_unbind;
- if ( (pirq < 0) || (pirq >= NR_PIRQS) )
+ if ( (pirq < 0) || (pirq >= NR_IRQS) )
return -EINVAL;
if ( !IS_PRIV(current->domain) )
spin_lock(&d->event_lock);
- for ( i = 0; i < NR_PIRQS; i++ )
+ for ( i = 0; i < NR_IRQS; i++ )
if ( d->arch.pirq_vector[i] > 0 )
unmap_domain_pirq(d, i);
struct dev_intx_gsi_link *digl;
int pirq = pt_irq_bind->machine_irq;
- if ( pirq < 0 || pirq >= NR_PIRQS )
+ if ( pirq < 0 || pirq >= NR_IRQS )
return -EINVAL;
spin_lock(&d->event_lock);
spin_lock(&d->event_lock);
pirq = hvm_irq_dpci->msi_gvec_pirq[vector];
- if ( ( pirq >= 0 ) && (pirq < NR_PIRQS) &&
+ if ( ( pirq >= 0 ) && (pirq < NR_IRQS) &&
test_bit(pirq, hvm_irq_dpci->mapping) &&
(test_bit(_HVM_IRQ_DPCI_MSI, &hvm_irq_dpci->mirq[pirq].flags)))
{
hvm_irq_dpci = domain_get_irq_dpci(d);
if ( hvm_irq_dpci != NULL )
{
- for ( i = find_first_bit(hvm_irq_dpci->mapping, NR_PIRQS);
- i < NR_PIRQS;
- i = find_next_bit(hvm_irq_dpci->mapping, NR_PIRQS, i + 1) )
+ for ( i = find_first_bit(hvm_irq_dpci->mapping, NR_IRQS);
+ i < NR_IRQS;
+ i = find_next_bit(hvm_irq_dpci->mapping, NR_IRQS, i + 1) )
{
pirq_guest_unbind(d, i);
kill_timer(&hvm_irq_dpci->hvm_timer[irq_to_vector(i)]);
return;
}
/* Multiple mirq may be mapped to one isa irq */
- for ( i = find_first_bit(dpci->mapping, NR_PIRQS);
- i < NR_PIRQS;
- i = find_next_bit(dpci->mapping, NR_PIRQS, i + 1) )
+ for ( i = find_first_bit(dpci->mapping, NR_IRQS);
+ i < NR_IRQS;
+ i = find_next_bit(dpci->mapping, NR_IRQS, i + 1) )
{
list_for_each_entry_safe ( digl, tmp,
&dpci->mirq[i].digl_list, list )
#define NR_VECTORS 256
#define VIOAPIC_NUM_PINS 48
-#define NR_PIRQS 256
#include <xen/hvm/irq.h>
#include <asm/hvm/vcpu.h>
#include <asm/hvm/domain.h>
#include <asm/e820.h>
-#include <asm/pirq.h>
#define has_32bit_shinfo(d) ((d)->arch.has_32bit_shinfo)
#define is_pv_32bit_domain(d) ((d)->arch.is_32bit_pv)
/* NB. protected by d->event_lock and by irq_desc[vector].lock */
int vector_pirq[NR_VECTORS];
- int pirq_vector[NR_PIRQS];
+ int pirq_vector[NR_IRQS];
/* Pseudophysical e820 map (XENMEM_memory_map). */
struct e820entry e820[3];
#ifndef __ASM_X86_HVM_IRQ_H__
#define __ASM_X86_HVM_IRQ_H__
-#include <asm/pirq.h>
#include <xen/hvm/irq.h>
#include <asm/hvm/hvm.h>
#include <asm/hvm/vpic.h>
+++ /dev/null
-#ifndef __XEN_PIRQ_H
-#define __XEN_PIRQ_H
-
-#define PIRQ_BASE 0
-#define NR_PIRQS 256
-
-#define DYNIRQ_BASE (PIRQ_BASE + NR_PIRQS)
-#define NR_DYNIRQS 256
-
-#endif /* __XEN_PIRQ_H */
-
/* Protected by domain's event_lock */
struct hvm_irq_dpci {
/* Machine IRQ to guest device/intx mapping. */
- DECLARE_BITMAP(mapping, NR_PIRQS);
+ DECLARE_BITMAP(mapping, NR_IRQS);
struct hvm_mirq_dpci_mapping mirq[NR_IRQS];
/* Guest IRQ to guest device/intx mapping. */
struct hvm_girq_dpci_mapping girq[NR_IRQS];